(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of eliminating a buried contact trench in the fabrication of integrated circuits.
(2) Description of the Prior Art
A buried contact is widely used in modern static random access memory (SRAM) processes to connect a polysilicon line to an active area. Referring to FIGS. 1-4, a typical buried contact process of the prior art will be described. FIG. 1 illustrates a partially completed integrated circuit device having a semiconductor substrate 10. An isolation region, such as Field OXide region 12 is formed as is conventional in the art. A layer of gate oxide 14 is grown or deposited over the surface of the substrate. A relatively thin layer of polysilicon 16 is deposited over the gate oxide layer 14. A photoresist mask 20 is used to pattern the polysilicon to form an opening over the planned buried contact. With the gate oxide as a protective layer, a vertical implant angle plug ion implantation 22 is performed to form the buried contact region 24. Usually, a quadrant angle tilt isolation implantation is performed to form a deeper isolation region 26 to isolation the plug implant from the surrounding region. Referring now to FIG. 2, the gate oxide layer 14 in the buried contact area is removed, then a second layer of polysilicon 28 is deposited which contacts the substrate through the buried contact opening. Next, the polysilicon is patterned. During the thermal cycle of the fabrication process, the plug implantation will diffuse laterally, about 0.05 microns, A. After lateral diffusion, the buried contact region will have a diffusion profile as illustrated by 25.
FIGS. 3 and 4 illustrate two potential problems affecting the function of the buried contact. Referring now to FIG. 3, there is illustrated a buried contact trench 32. The overlap of polysilicon 28 to the buried contact region 24 normally is less than about 0.05 microns. The misalignment, or overlay, of the stepper used in photolithography usually is less than 0.10 microns, depending upon the machine specification. If the misalignment causes the polysilicon pattern not to fully cover the buried contact opening, as shown in FIG. 3 (that is, the photomask 30 is shifted to the left), the substrate will be etched into during the polysilicon etch resulting in the buried contact trench 32. This is because the etch selectivity of polysilicon to the substrate silicon is very low. The trench causes a poor connection and increased junction leakage. If the trench is deep enough, it will break through the junction.
FIG. 4 illustrates a second potential misalignment problem. If the misalignment of the photoresist mask 30 causes the polysilicon to overlap the buried contact by too much (that is, the photomask 30 is shifted to the right), a disconnection gap 34 may occur. After etching of the polysilicon 28, a source/drain implantation is performed to form source/drain region 27. The source/drain region 27 should contact the buried contact region 25. However, because of misalignment, even with lateral diffusion of the source/drain region 27, there is a gap 34 between the source/drain region 27 and the buried contact region 35. Disconnection results in device failure. Therefore, this error is to be avoided at all costs. Workers in the art would rather have a small trench than to have a disconnection gap. Thus, the overlap of polysilicon to buried contact on the mask is usually set to be 0 to 0.05 microns. Since the layer to layer misalignment of a stepper is around 0.10 microns, this means that a buried contact trench will always be formed. The existence of the trench dramatically reduces the process margin of the polysilicon etch, thus reducing chip yield.
Various inventions have been made to prevent the formation of a buried contact trench, to fill a buried contact trench so that a current path is maintained, or to bridge a disconnection gap. For example, U.S. Pat. No. 5,494,848 to H. W. Chin teaches a method using an oversized mask to protect the buried junction area during overetch so that a misalignment of the mask will not cause the formation of a buried contact trench. U.S. Pat. No. 5,596,215 to Huang teaches forming spacers on the sidewalls of the gate structures to fill the buried contact trench and form a current path. U.S. Pat. No. 5,607,881 to Huang teaches linking the buried contact junction and the source junction by an extra high dose N+ implant to overcome the disadvantages of a buried contact trench. U.S. Pat. No. 5,378,641 to Cheffings teaches a two-step angled implant to form the buried contact and a substrate interconnect between the buried contact and the source/drain region. U.S. Pat. No. 5,581,093 to Sakamoto teaches another method of forming a buried contact.
Large tilt angle ion implantation and tapered polysilicon gates have been used in the art. For example, U.S. Pat. No. 5,593,922 to Liaw et al teaches a channel stop implant using large angle tilt in order to isolate closely spaced buried contact junctions. In the paper, "Managing Implant Shadowing," by D. Abercrombie et al, Semiconductor International, September 1996, pp. 107-109, the authors show that a 7 degree tilt angle source/drain implant around a tapered polysilicon gate produces symmetrical source/drain implants while a vertical polysilicon gate results in shadowing; non-symmetrical source/drain implants.